RERIEN=DISABLED, ROREI=NOT_SET, MATMD=OFF, TEN=DISABLED, RINH=INACTIVE, ROSEN=DISABLED, RDREQI=NOT_SET, TBUSYF=NOT_SET, TBIT=NOT_SET, TCPTI=NOT_SET, TCPTIEN=DISABLED, REN=DISABLED, TERIEN=DISABLED, TSCERI=NOT_SET, RBIT=NOT_SET, RABDEN=DISABLED, TINH=INACTIVE, TDREQI=NOT_SET, RFRMERI=NOT_SET, TCPTTH=SET_ON_TX, RBUSYF=NOT_SET, RPARERI=NOT_SET, TDREQIEN=DISABLED, RDREQIEN=DISABLED
Module Control
| RFRMERI | Receive Frame Error Interrupt Flag. 0 (NOT_SET): Read: A frame error has not occurred since RFRMERI was last cleared. Write: Clear the interrupt. 1 (SET): Read: A frame error occurred. Write: Force a frame error interrupt. |
| RPARERI | Receive Parity Error Interrupt Flag. 0 (NOT_SET): Read: An invalid parity bit has not been received since RPARERI was last cleared. Write: Clear the interrupt. 1 (SET): Read: An invalid parity bit has been received since RPARERI was last cleared. Write: Force a parity error interrupt. |
| ROREI | Receive Overrun Error Interrupt Flag. 0 (NOT_SET): Read: A receiver overrun has not occurred since ROREI was last cleared. Write: Clear the interrupt. 1 (SET): Read: A receiver overrun occurred. Write: Force a receiver overrun interrupt. |
| RDREQI | Receive Data Request Interrupt Flag. 0 (NOT_SET): Fewer than RFTH FIFO slots are filled with data. 1 (SET): At least RFTH FIFO slots are filled with data. |
| RERIEN | Receive Error Interrupt Enable. 0 (DISABLED): Disable the receive error interrupt. 1 (ENABLED): Enable the receive error interrupt. A receive error interrupt is asserted when ROREI, RFRMERI, or RPARERI is set to 1. |
| RDREQIEN | Receive Data Request Interrupt Enable. 0 (DISABLED): Disable the read data request interrupt. 1 (ENABLED): Enable the read data request interrupt. A receive interrupt is generated when RDREQI is set to 1. |
| MATMD | Match Mode. 0 (OFF): Disable the match function. 1 (MCE): (MCE) Data whose last data bit equals RBIT is accepted and stored. 2 (FRAME): (Frame) A framing error is asserted if the last received bit matches RBIT. 3 (STORE): (Store) Store the last incoming data bit in RBIT. This mode can be used inconjunction with the RDATLN setting. |
| RABDEN | Receiver Auto-Baud Enable. 0 (DISABLED): Disable receiver auto-baud. 1 (ENABLED): Enable receiver auto-baud. |
| RBUSYF | Receiver Busy Flag. 0 (NOT_SET): The UART receiver is idle. 1 (SET): The UART receiver is receiving data. |
| RBIT | Last Receive Bit. 0 (NOT_SET): undefined 1 (SET): undefined |
| ROSEN | Receiver One-Shot Enable. 0 (DISABLED): Disable one-shot receive mode. 1 (ENABLED): Enable one-shot receive mode. |
| RINH | Receiver Inhibit. 0 (INACTIVE): The receiver operates normally. 1 (ACTIVE): RTS is immediately asserted when RINH is set. The receiver will complete any ongoing reception, but ignore all traffic after that. |
| REN | Receiver Enable. 0 (DISABLED): Disable the receiver. The receiver can receive one data transaction only if ROSEN is set. 1 (ENABLED): Enable the receiver. |
| TSCERI | Smartcard Parity Error Interrupt Flag. 0 (NOT_SET): Read: A Smartcard parity error has not occurred since TSCERI was last cleared. Write: Clear the interrupt. 1 (SET): Read: A Smartcard parity error occurred. Write: Force a Smartcard parity error interrupt. |
| TDREQI | Transmit Data Request Interrupt Flag. 0 (NOT_SET): The transmitter is not requesting more FIFO data. 1 (SET): The transmitter is requesting more FIFO data. |
| TCPTI | Transmit Complete Interrupt Flag. 0 (NOT_SET): Read: A transmit has not completed since TCPTI was last cleared. Write: Clear the interrupt. 1 (SET): Read: A byte was transmitted (TCCPTH = 0) or the last available byte was transmitted (TCPTTH = 1). Write: Force a transmit complete interrupt. |
| TCPTTH | Transmit Complete Threshold. 0 (SET_ON_TX): A transmit is completed (TCPTI = 1) at the end of each transmission. 1 (SET_ON_EMPTY): A transmit is completed (TCPTI = 1) only at the end of a transmission when no more data is available to transmit. |
| TERIEN | Transmit Error Interrupt Enable. 0 (DISABLED): Disable the transmit error interrupt. 1 (ENABLED): Enable the transmit error interrupt. A transmit interrupt is generated when TUREI or TSCERI is set to 1. |
| TDREQIEN | Transmit Data Request Interrupt Enable. 0 (DISABLED): Disable the transmit data request interrupt. 1 (ENABLED): Enable the transmit data request interrupt. A transmit interrupt is asserted when TDREQI is set to 1. |
| TCPTIEN | Transmit Complete Interrupt Enable. 0 (DISABLED): Disable the transmit complete interrupt. 1 (ENABLED): Enable the transmit complete interrupt. A transmit interrupt is generated when TCPTI is set to 1. |
| TBUSYF | Transmitter Busy Flag. 0 (NOT_SET): The UART transmitter is idle. 1 (SET): The UART transmitter is active and transmitting. |
| TBIT | Last Transmit Bit. 0 (NOT_SET): undefined 1 (SET): undefined |
| TINH | Transmit Inhibit. 0 (INACTIVE): The transmitter operates normally. 1 (ACTIVE): Transmissions are inhibited. The transmitter will stall after any current transmission is complete. |
| TEN | Transmitter Enable. 0 (DISABLED): Disable the transmitter. When cleared, the transmitter immediately aborts any active transmission. Clearing this bit does not automatically flush the transmit FIFO. 1 (ENABLED): Enable the transmitter. The transmitter will initiate a transmission when data becomes available in the transmit FIFO. |